A frequency synthesizer is an electronic circuit that generates any of a range of output frequencies from an input signal typically having a single fixed frequency. Frequency synthesizers are used in a wide range of applications, such as in the transceivers of mobile phones and radios and wireless network equipment. Data to be transmitted by these devices modulates a radio frequency (RF) carrier signal in the transmitter portion of a transceiver in the transmitting device and the modulated signal is transmitted. The modulated signal is received and demodulated in the receiver portion of a transceiver in the receiving device. In order to correctly modulate and demodulate the signal, an accurate RF carrier signal must be generated in the transmitting and receiving devices. The frequency synthesizer is used to generate the RF carrier signal to be modulated by the data and demodulated to recover the data, typically based on a local oscillator that oscillates at a stable frequency. One typical type of frequency synthesizer includes a phase-locked loop (PLL) that produces an output at a frequency that is at an integer multiple of the input signal from the local oscillator. An integer-multiple PLL typically includes a phase detector (PD), voltage controlled oscillator (VCO), and a divider. The phase detector compares the input signal with a feedback signal and produces an error signal that is used to control the VCO. By connecting a divider between the output of the VCO and the feedback input of the phase detector, the phase detector attempts to keep the divided feedback signal in phase with the input signal, thereby producing an output from the VCO at an integer multiple of the input frequency. As a result, the frequency resolution of an integer-N PLL is equal to the input frequency. An integer-N PLL with a relatively high input frequency suffers from poor output frequency resolution. An integer-N PLL with a low reference frequency used to provide fine output frequency resolution suffers from a long lock time due to narrow loop bandwidth and a large divide ratio that increases in-band phase noise.
One solution to these disadvantages is the use of a fractional-N PLL, based on a fractional-N divider. In a fractional-N divider, the divider alternates between divide ratios. For example, by alternating between dividing by 5 and 6, the output frequency would be 5.5 times the input frequency. However, this can cause noise spurs at the frequency at which the divider ratio is switched. In the example above where the divider ratio is switched every period of the input signal, the noise spur would be at ½ the input frequency. The noise spur moves to an even lower frequency when the divider ratio is closer to an integer number, such as 5.01, when the divider would divide by five 99 times and by six 1 time, moving the fractional noise to 1/100 of the input frequency. Low frequency noise generated by the fractional-N divider is not filtered effectively by the PLL because it is typically well below the loop bandwidth of the PLL, causing jitter on the output.
A delta sigma (As) modulator shifts the divider noise to higher frequencies where it can be filtered out by the PLL. The delta sigma modulator (DSM) changes or modulates the divider ratio between multiple different ratios while placing the average value at the desired divider ratio. The divider ratio is typically changed every few cycles to keep the noise spur at as high a frequency as possible so that it can be filtered by the PLL. Instead of alternating only between divider ratios of 5 and 6, the DSM may alternate between divider ratios of, for example, any integer ratio between 2 and 8, while placing the average value at the desired ratio of 5.5. By alternating frequently between a greater range of divider ratios, the noise is elevated to a higher frequency. However, a need remains for further noise reduction techniques.